%O cited By 2
%L scholars3765
%J IEEE Sensors Journal
%D 2013
%R 10.1109/JSEN.2012.2224331
%N 2
%X An interface circuit design for an optical sensor based on a two-stage cascaded architecture is presented in this paper. The proposed design is a mixed signal solution that provides few advantages in terms of speed, power consumption, higher resolution with smaller number of storage units, and small area for future on-chip integration. Simulation and experimental results for five bits resolution (32 levels) are presented to validate the design. We are aiming for a single-chip integrated solution; however, for a quick proof of concept, the proposed design has been implemented as a PCB using discrete off-the-shelf components. The biasing current and power consumption from the PCB implementation are 192 mA and 1.3 W, respectively, at a 6.75-V supply voltage. © 2001-2012 IEEE.
%K Biasing current; Higher resolution; Integrated solutions; Interface circuits; Mixed signal; Off-the-shelf components; On-chip integration; Proof of concept; Single-chip; Small area; Storage units; Supply voltages, Design; Optical sensors; Organic pollutants; Polychlorinated biphenyls, Logic circuits
%P 610-617
%T Two-stage interface circuit design for a 32-color resolution optical sensor
%V 13
%A M. Assaad
%A I. Yohannes
%A A. Bermak