TY  - JOUR
SN  - 1530437X
EP  - 617
AV  - none
TI  - Two-stage interface circuit design for a 32-color resolution optical sensor
SP  - 610
N1  - cited By 2
Y1  - 2013///
VL  - 13
JF  - IEEE Sensors Journal
A1  - Assaad, M.
A1  - Yohannes, I.
A1  - Bermak, A.
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-84872297914&doi=10.1109%2fJSEN.2012.2224331&partnerID=40&md5=b2921eb715dd96dc065ba3e0e6651c52
ID  - scholars3765
KW  - Biasing current; Higher resolution; Integrated solutions; Interface circuits; Mixed signal; Off-the-shelf components; On-chip integration; Proof of concept; Single-chip; Small area; Storage units; Supply voltages
KW  -  Design; Optical sensors; Organic pollutants; Polychlorinated biphenyls
KW  -  Logic circuits
N2  - An interface circuit design for an optical sensor based on a two-stage cascaded architecture is presented in this paper. The proposed design is a mixed signal solution that provides few advantages in terms of speed, power consumption, higher resolution with smaller number of storage units, and small area for future on-chip integration. Simulation and experimental results for five bits resolution (32 levels) are presented to validate the design. We are aiming for a single-chip integrated solution; however, for a quick proof of concept, the proposed design has been implemented as a PCB using discrete off-the-shelf components. The biasing current and power consumption from the PCB implementation are 192 mA and 1.3 W, respectively, at a 6.75-V supply voltage. © 2001-2012 IEEE.
IS  - 2
ER  -