relation: https://khub.utp.edu.my/scholars/3765/
title: Two-stage interface circuit design for a 32-color resolution optical sensor
creator: Assaad, M.
creator: Yohannes, I.
creator: Bermak, A.
description: An interface circuit design for an optical sensor based on a two-stage cascaded architecture is presented in this paper. The proposed design is a mixed signal solution that provides few advantages in terms of speed, power consumption, higher resolution with smaller number of storage units, and small area for future on-chip integration. Simulation and experimental results for five bits resolution (32 levels) are presented to validate the design. We are aiming for a single-chip integrated solution; however, for a quick proof of concept, the proposed design has been implemented as a PCB using discrete off-the-shelf components. The biasing current and power consumption from the PCB implementation are 192 mA and 1.3 W, respectively, at a 6.75-V supply voltage. © 2001-2012 IEEE.
date: 2013
type: Article
type: PeerReviewed
identifier:   Assaad, M. and Yohannes, I. and Bermak, A.  (2013) Two-stage interface circuit design for a 32-color resolution optical sensor.  IEEE Sensors Journal, 13 (2).  pp. 610-617.  ISSN 1530437X     
relation: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84872297914&doi=10.1109%2fJSEN.2012.2224331&partnerID=40&md5=b2921eb715dd96dc065ba3e0e6651c52
relation: 10.1109/JSEN.2012.2224331
identifier: 10.1109/JSEN.2012.2224331