eprintid: 3316
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/33/16
datestamp: 2023-11-09 15:51:34
lastmod: 2023-11-09 15:51:34
status_changed: 2023-11-09 15:46:33
type: conference_item
metadata_visibility: show
creators_name: Anggraeni, S.
creators_name: Hussin, F.A.
creators_name: Jeoti, V.
title: High throughput architecture for low density parity check (LDPC) encoder
ispublished: pub
keywords: Code length; High throughput; Ieee 802.16e standards; Low density parity check; Matrix vector multiplication; Proposed architectures
note: cited By 1; Conference of 2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013 ; Conference Date: 4 August 2013 Through 7 August 2013; Conference Code:102320
abstract: This paper proposes a bit-wise matrix-vector multiplication in the optimization of a proposed low density parity check (LDPC) encoder. Investigation of this proposed architecture is done by implementing five code lengths using one IEEE 802.16e standard code rate. It is shown that the proposed architecture outperforms other works in terms of information throughput ranging from 0.235 to 8.83 times higher. In term of ratio of throughput per area, the proposed method exceeds other works in the range of 1.19 to 6.54 times higher. © 2013 IEEE.
date: 2013
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84893175011&doi=10.1109%2fMWSCAS.2013.6674807&partnerID=40&md5=f7572e89e63b24d3968cc90517b9a2a3
id_number: 10.1109/MWSCAS.2013.6674807
full_text_status: none
publication: Midwest Symposium on Circuits and Systems
place_of_pub: Columbus, OH
pagerange: 948-951
refereed: TRUE
isbn: 9781479900664
issn: 15483746
citation:   Anggraeni, S. and Hussin, F.A. and Jeoti, V.  (2013) High throughput architecture for low density parity check (LDPC) encoder.  In: UNSPECIFIED.