relation: https://khub.utp.edu.my/scholars/3316/
title: High throughput architecture for low density parity check (LDPC) encoder
creator: Anggraeni, S.
creator: Hussin, F.A.
creator: Jeoti, V.
description: This paper proposes a bit-wise matrix-vector multiplication in the optimization of a proposed low density parity check (LDPC) encoder. Investigation of this proposed architecture is done by implementing five code lengths using one IEEE 802.16e standard code rate. It is shown that the proposed architecture outperforms other works in terms of information throughput ranging from 0.235 to 8.83 times higher. In term of ratio of throughput per area, the proposed method exceeds other works in the range of 1.19 to 6.54 times higher. © 2013 IEEE.
date: 2013
type: Conference or Workshop Item
type: PeerReviewed
identifier:   Anggraeni, S. and Hussin, F.A. and Jeoti, V.  (2013) High throughput architecture for low density parity check (LDPC) encoder.  In: UNSPECIFIED.     
relation: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84893175011&doi=10.1109%2fMWSCAS.2013.6674807&partnerID=40&md5=f7572e89e63b24d3968cc90517b9a2a3
relation: 10.1109/MWSCAS.2013.6674807
identifier: 10.1109/MWSCAS.2013.6674807