TY  - JOUR
N2  - A side gate p-type junctionless silicon transistor is fabricated by atomic force microscopy nanolithography using a anisotropic potassium hydroxide wet etching process on low doped (10 5cm -3) silicon-on-insulator wafer. The structure is a gated resistor and turns off based on a pinch-off effect principle, when essential positive gate voltage is applied and made a sufficiently large barrier in the gating region. Negative gate voltage is unable to make a significant impact on drain current to drive the device into accumulation mode. The experimental transfer characteristic is investigated and compared with the simulation result for positive gate voltage. 'On/off' ratio and subthreshold swing were also measured. The numerical study of the device in 'off' state is investigated based on the variation of majority and minority carriers' density and recombination generation in the active region of the device, which offers more understanding of the device operation and also for previous works. © 2012 The Institution of Engineering and Technology.
IS  - 9
ID  - scholars2903
KW  - Accumulation modes; Active regions; Device operations; Gate voltages; Junctionless; Minority carrier; Negative gate voltages; Numerical investigations; Numerical studies; P-type; Pinchoff; Side gate; Significant impacts; Silicon on insulator wafers; Silicon transistors; Subthreshold swing; Transfer characteristics
KW  -  Atomic force microscopy; Potassium hydroxide; Wet etching
KW  -  Silicon wafers
KW  -  potassium hydroxide; silicon
KW  -  article; atomic force microscopy; controlled study; electric potential; geometry; measurement; nanofabrication; scanning electron microscopy; semiconductor; side gate p type junctionless silicon transistor; simulation
Y1  - 2012///
A1  - Dehzangi, A.
A1  - Larki, F.
A1  - Hutagalung, S.D.
A1  - Saion, E.B.
A1  - Abdullah, A.M.
A1  - Hamidon, M.N.
A1  - Majlis, B.Y.
A1  - Kakooei, S.
A1  - Navaseri, M.
A1  - Kharazmi, A.
JF  - Micro and Nano Letters
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-84867156543&doi=10.1049%2fmnl.2012.0590&partnerID=40&md5=c650b5f3761014b887f3eb1686f5a898
VL  - 7
AV  - none
N1  - cited By 11
SP  - 981
TI  - Numerical investigation and comparison with experimental characterisation of side gate p-type junctionless silicon transistor in pinch-off state
SN  - 17500443
EP  - 985
ER  -