TY  - CONF
KW  - Co-processors; Computation power; Data-path architecture; Frame rate; Frames per seconds; Hardware accelerators; Memory access; Memory bandwidths; New applications; Parallel and pipeline; Read operation; Real time; Real time performance; Real-time video segmentation; Sobel edge detection; Standard definitions; Video image processing; Video rates; Video segmentation; Video surveillance systems; VLSI
KW  -  Digital signal processors; Edge detection; Field programmable gate arrays (FPGA); Hardware; Image segmentation; Memory architecture; Security systems; Signal processing
KW  -  Information management
TI  - VLSI based edge detection hardware accelerator for real time video segmentation system
ID  - scholars2763
SP  - 719
N1  - cited By 6; Conference of 2012 4th International Conference on Intelligent and Advanced Systems, ICIAS 2012 ; Conference Date: 12 June 2012 Through 14 June 2012; Conference Code:93534
N2  - Video segmentation is one of video image processing application that deployed by video surveillance system. The high computation power must be provided to support real time performance. This paper presents the implementation of VLSI based hardware accelerator design for real time video segmentation system. The algorithm of Sobel edge detection operator is used to develop this hardware accelerator. The NTSC standard definition video is digitized at 720�480 with a video rate of 30 frames per second. To develop hardware accelerator datapath architecture the management of memory access is deployed and architecture based pipeline are made with the potential improvements in acceleration to the read data pixel from memory. In addition, a finite state machine is used to ensure the hardware accelerator controls the sequence of derivative computation, the write and read operations. The hardware accelerator design is implemented on Altera Stratix III DSP development board and enables application of co-processor without requiring new application specific digital signal processor. The implementation result shows a field programmable gate arrays (FPGAs) acting as coprocessor platforms for user defined co-processor, with real time performance at a frame rate of 30 fps with a resolution of 720 � 480. The parallel and pipeline technique are utilized in memory access, resulting more than 70 memory bandwidth reduction. © 2011 IEEE.
AV  - none
CY  - Kuala Lumpur
VL  - 2
EP  - 724
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-84867925720&doi=10.1109%2fICIAS.2012.6306107&partnerID=40&md5=52588b51fe6b1b3e3dc6ee682e94b7f6
A1  - Yasri, I.
A1  - Hamid, N.H.
A1  - Ali, N.B.Z.
SN  - 9781457719677
Y1  - 2012///
ER  -