eprintid: 2732
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/27/32
datestamp: 2023-11-09 15:50:58
lastmod: 2023-11-09 15:50:58
status_changed: 2023-11-09 15:44:09
type: article
metadata_visibility: show
creators_name: Assaad, M.
creators_name: Alser, M.H.
title: Design of an all-digital synchronized frequency multiplier based on a dual-loop (D/FLL) architecture
ispublished: pub
keywords: Clock signal; Frequency multiplier; Frequency steps; Frequency-locked-loop; Higher frequencies; Jitter accumulation; Logic elements; Phase tracking; Proposed architectures; Reference signals; System-On-Chip; Verilog, Application specific integrated circuits; Clocks; Computer hardware description languages; Field programmable gate arrays (FPGA); Frequency multiplying circuits, Digital integrated circuits
note: cited By 5
abstract: This paper presents a new architecture for a synchronized frequency multiplier circuit. The proposed architecture is an all-digital dual-loop delay- and frequency-locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered in PLL and can be adapted easily for different FPGA families as well as implemented as an integrated circuit. Moreover, it can be used in supplying a clock reference for distributed digital processing systems as well as intra/interchip communication in system-on-chip (SoC). The proposed architecture is designed using the Verilog language and synthesized for the Altera DE2-70 development board. The experimental results validate the expected phase tracking as well as the synthesizing properties. For the measurement and validation purpose, an input reference signal in the range of 1.942.62 MHz was injected; the generated clock signal has a higher frequency, and it is in the range of 124.2167.9 MHz with a frequency step (i.e., resolution) of 0.168 MHz. The synthesized design requires 330 logic elements using the above Altera board. © 2012 Maher Assaad and Mohammed H. Alser.
date: 2012
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84867951248&doi=10.1155%2f2012%2f546212&partnerID=40&md5=d08c24bab96c096c00be885c9c154657
id_number: 10.1155/2012/546212
full_text_status: none
publication: VLSI Design
volume: 2012
refereed: TRUE
issn: 1065514X
citation:   Assaad, M. and Alser, M.H.  (2012) Design of an all-digital synchronized frequency multiplier based on a dual-loop (D/FLL) architecture.  VLSI Design, 2012.   ISSN 1065514X