relation: https://khub.utp.edu.my/scholars/2731/
title: Performance comparison review of Radix-based multiplier designs
creator: Swee, K.L.S.
creator: Hiung, L.H.
description: This is a study of the relative performance comparison of Radix-based Booth Encoding multiplier. Multipliers included in the comparison are Radix-2 Booth Encoding multiplier, Radix-4 Booth Encoding multiplier, Radix-8 Booth Encoding multiplier, Radix-16 Booth Encoding multiplier and Radix-32 Booth Encoding multiplier. All these multiplier designs were modeled in Verilog HDL and synthesized based on TSMC 0.35-micron ASIC Design Kit standard cell library. The performance data was extracted after logic synthesis has been done by using Leonardo Spectrum for Area, Speed and Auto-Optimization modes. From the findings obtained, it is known that the gate level and delay synthesis performances of the Radix-4 Booth Encoding multiplier are reduced if it is compared to Radix-2 Booth Encoding multiplier design. Then, as the higher the number of Radix-based multiplier, both the gate level and the delay performances will increase due to the complexity of the partial products encoded. However, the largest area and longest timing delay can still be seen in Radix-2 Booth Encoding multiplier. The comparison of the 32-bit Radix-based Booth Encoding variants indicates that the Radix-4 Booth Encoding multiplier is the best multiplier in terms of high-speed applications and low area constraint. © 2011 IEEE.
date: 2012
type: Conference or Workshop Item
type: PeerReviewed
identifier:   Swee, K.L.S. and Hiung, L.H.  (2012) Performance comparison review of Radix-based multiplier designs.  In: UNSPECIFIED.     
relation: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84867952023&doi=10.1109%2fICIAS.2012.6306134&partnerID=40&md5=5cf223ec4141af7d31feff4d393eb695
relation: 10.1109/ICIAS.2012.6306134
identifier: 10.1109/ICIAS.2012.6306134