@inproceedings{scholars2731,
             doi = {10.1109/ICIAS.2012.6306134},
          volume = {2},
            note = {cited By 22; Conference of 2012 4th International Conference on Intelligent and Advanced Systems, ICIAS 2012 ; Conference Date: 12 June 2012 Through 14 June 2012; Conference Code:93534},
         address = {Kuala Lumpur},
           title = {Performance comparison review of Radix-based multiplier designs},
            year = {2012},
           pages = {854--859},
         journal = {ICIAS 2012 - 2012 4th International Conference on Intelligent and Advanced Systems: A Conference of World Engineering, Science and Technology Congress (ESTCON) - Conference Proceedings},
        abstract = {This is a study of the relative performance comparison of Radix-based Booth Encoding multiplier. Multipliers included in the comparison are Radix-2 Booth Encoding multiplier, Radix-4 Booth Encoding multiplier, Radix-8 Booth Encoding multiplier, Radix-16 Booth Encoding multiplier and Radix-32 Booth Encoding multiplier. All these multiplier designs were modeled in Verilog HDL and synthesized based on TSMC 0.35-micron ASIC Design Kit standard cell library. The performance data was extracted after logic synthesis has been done by using Leonardo Spectrum for Area, Speed and Auto-Optimization modes. From the findings obtained, it is known that the gate level and delay synthesis performances of the Radix-4 Booth Encoding multiplier are reduced if it is compared to Radix-2 Booth Encoding multiplier design. Then, as the higher the number of Radix-based multiplier, both the gate level and the delay performances will increase due to the complexity of the partial products encoded. However, the largest area and longest timing delay can still be seen in Radix-2 Booth Encoding multiplier. The comparison of the 32-bit Radix-based Booth Encoding variants indicates that the Radix-4 Booth Encoding multiplier is the best multiplier in terms of high-speed applications and low area constraint. {\^A}{\copyright} 2011 IEEE.},
        keywords = {ASIC design; Booth encoding; Delay performance; Gate levels; High-speed applications; Leonardo spectrum; Logic synthesis; Low area; Multiplier design; Partial product; Performance comparison; Performance data; Radix 2; Radix-4; Relative performance; Standard cell; Timing delay; Verilog HDL, Design; Digital arithmetic; Electric batteries; Integrated circuits, Multiplying circuits},
             url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-84867952023&doi=10.1109\%2fICIAS.2012.6306134&partnerID=40&md5=5cf223ec4141af7d31feff4d393eb695},
            isbn = {9781457719677},
          author = {Swee, K. L. S. and Hiung, L. H.}
}