relation: https://khub.utp.edu.my/scholars/2728/
title: Design and FPGA implementation of PLL-based quarter-rate clock and data recovery circuit
creator: Alser, M.H.
creator: Assaad, M.
creator: Hussin, F.A.
creator: Yohannes, I.
description: This paper overviews the increased dynamic power consumption issue associated with the use of the serial links as a medium of data communication in today's multi-module based system-on-chip (SoC) and presents a novel all-digital PLL-based quarter-rate clock and data recovery circuit as a potential solution. The proposed architecture works at a frequency equal to one-fourth the received data rate and utilizes a quarter-rate early-late type phase detector, a delay line, a delay line controller, and a digitally controlled oscillator (DCO)-based 8-phases generator. The proposed architecture can be adapted easily for different FPGA families, as well as implemented as an integrated circuit. Moreover, it can be used in a deserializer as part of a SERDES in inter-module communication in SoC. The proposed architecture is designed using the Verilog language and synthesized for the Altera DE2-70 development board. Furthermore, the simulation results validate the expected functionality, such as performing quarter-rate phase detection as well as 1-to-4 demultiplexing. The synthesized design requires 117 logic elements using the above Altera board. © 2011 IEEE.
date: 2012
type: Conference or Workshop Item
type: PeerReviewed
identifier:   Alser, M.H. and Assaad, M. and Hussin, F.A. and Yohannes, I.  (2012) Design and FPGA implementation of PLL-based quarter-rate clock and data recovery circuit.  In: UNSPECIFIED.     
relation: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84867955076&doi=10.1109%2fICIAS.2012.6306128&partnerID=40&md5=6146e34b1a4874a7b2f6a4482f976cd4
relation: 10.1109/ICIAS.2012.6306128
identifier: 10.1109/ICIAS.2012.6306128