@inproceedings{scholars2728,
          volume = {2},
            note = {cited By 2; Conference of 2012 4th International Conference on Intelligent and Advanced Systems, ICIAS 2012 ; Conference Date: 12 June 2012 Through 14 June 2012; Conference Code:93534},
             doi = {10.1109/ICIAS.2012.6306128},
         address = {Kuala Lumpur},
           title = {Design and FPGA implementation of PLL-based quarter-rate clock and data recovery circuit},
            year = {2012},
         journal = {ICIAS 2012 - 2012 4th International Conference on Intelligent and Advanced Systems: A Conference of World Engineering, Science and Technology Congress (ESTCON) - Conference Proceedings},
           pages = {825--830},
        abstract = {This paper overviews the increased dynamic power consumption issue associated with the use of the serial links as a medium of data communication in today's multi-module based system-on-chip (SoC) and presents a novel all-digital PLL-based quarter-rate clock and data recovery circuit as a potential solution. The proposed architecture works at a frequency equal to one-fourth the received data rate and utilizes a quarter-rate early-late type phase detector, a delay line, a delay line controller, and a digitally controlled oscillator (DCO)-based 8-phases generator. The proposed architecture can be adapted easily for different FPGA families, as well as implemented as an integrated circuit. Moreover, it can be used in a deserializer as part of a SERDES in inter-module communication in SoC. The proposed architecture is designed using the Verilog language and synthesized for the Altera DE2-70 development board. Furthermore, the simulation results validate the expected functionality, such as performing quarter-rate phase detection as well as 1-to-4 demultiplexing. The synthesized design requires 117 logic elements using the above Altera board. {\^A}{\copyright} 2011 IEEE.},
        keywords = {Clock and data recovery; Deserializers; Phase detectors; Serializers; System-On-Chip, Application specific integrated circuits; Clocks; Computer hardware description languages; Field programmable gate arrays (FPGA); Programmable logic controllers; Signal detection; Waves, Antenna phased arrays},
             url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-84867955076&doi=10.1109\%2fICIAS.2012.6306128&partnerID=40&md5=6146e34b1a4874a7b2f6a4482f976cd4},
            isbn = {9781457719677},
          author = {Alser, M. H. and Assaad, M. and Hussin, F. A. and Yohannes, I.}
}