@inproceedings{scholars2726,
           title = {Performance comparison review of 32-bit multiplier designs},
         address = {Kuala Lumpur},
            note = {cited By 24; Conference of 2012 4th International Conference on Intelligent and Advanced Systems, ICIAS 2012 ; Conference Date: 12 June 2012 Through 14 June 2012; Conference Code:93534},
          volume = {2},
             doi = {10.1109/ICIAS.2012.6306130},
         journal = {ICIAS 2012 - 2012 4th International Conference on Intelligent and Advanced Systems: A Conference of World Engineering, Science and Technology Congress (ESTCON) - Conference Proceedings},
           pages = {836--841},
            year = {2012},
             url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-84867955816&doi=10.1109\%2fICIAS.2012.6306130&partnerID=40&md5=1b5e1f95f87184014ba4f387d6827cf4},
        keywords = {Array multipliers; Booth encoding; Dadda multipliers; Logic synthesis; Reduced-area multiplier; Wallace multiplier, Design; Digital arithmetic; Electric batteries; Integrated circuits; Optimization; Speed; Time delay, Multiplying circuits},
        abstract = {This is a study of a relative performance comparison of various 32-bits multiplier designs of Array, Wallace, Dadda, Reduced Area and Radix-4 Booth Encoding multipliers in the Area-Optimized, Speed-Optimized and Auto-Optimized synthesis modes in Leonardo Spectrum. These multiplier designs were modeled in Verilog HDL, simulated in Modelsim and synthesized based on TSMC 0.35-micron ASIC Design Kit standard cell library. We were able to conclude that Radix-4 Booth Encoding multiplier has the best findings in the area performance in all three of the Area-Optimized, Speed-Optimized and Auto-Optimized mode. In the Speed-Optimized mode, we found out that the findings were different from the results obtained when synthesized in the Area-Optimized and Auto-Optimization mode where Wallace multiplier exhibited the largest area performance instead of Dadda multiplier in the Speed-Optimized mode. The result showed the same findings for the delay performance when the designs were synthesized in the Area-Optimized and Auto-Optimized mode where it is known that Array multiplier experienced the longest time delay performance while Dadda multiplier exhibits the shortest time delay in terms of speed. However, when the Speed-Optimized mode is used, it showed that the Array multiplier has the longest delay while the fastest in terms of speed performance is produced by Wallace multiplier. {\^A}{\copyright} 2011 IEEE.},
          author = {Swee, K. L. S. and Hiung, L. H.},
            isbn = {9781457719677}
}