eprintid: 2700 rev_number: 2 eprint_status: archive userid: 1 dir: disk0/00/00/27/00 datestamp: 2023-11-09 15:50:56 lastmod: 2023-11-09 15:50:56 status_changed: 2023-11-09 15:44:05 type: conference_item metadata_visibility: show creators_name: Anggraeni, S. creators_name: Hussin, F.A. creators_name: Jeoti, V. title: Pipelined architecture for low density parity check encoder ispublished: pub keywords: encoder; Exclusive-OR; Information bit; Low density parity check; Parity check matrices; Pipelined architecture; Proposed architectures; Sub-matrices, Architecture; Matrix algebra; Pipe linings; Shift registers, Pipeline processing systems note: cited By 0; Conference of 2012 4th International Conference on Intelligent and Advanced Systems, ICIAS 2012 ; Conference Date: 12 June 2012 Through 14 June 2012; Conference Code:93534 abstract: This paper proposes a pipelined architecture for low density parity check encoder by pipelining information bits and sub-matrices of parity check matrix (H) using two bit-wise operations. The two bit-wise operations are multiplication and exclusive-OR. The investigation is done by exploring two methods of pipelining using the two bit-wise operations in the proposed architecture. The first method of pipelining uses combination of shift register and memory for the sub-matrices of H while the second method of pipelining uses shift register for the information bits and the sub-matrices of H. It is shown that the second method of pipelining increases the throughput but has the largest units of shift registers and flip-flops in the design. © 2011 IEEE. date: 2012 official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84867972450&doi=10.1109%2fICIAS.2012.6306129&partnerID=40&md5=da61cebc4d9584bfe8e99e2ed02dd9a9 id_number: 10.1109/ICIAS.2012.6306129 full_text_status: none publication: ICIAS 2012 - 2012 4th International Conference on Intelligent and Advanced Systems: A Conference of World Engineering, Science and Technology Congress (ESTCON) - Conference Proceedings volume: 2 place_of_pub: Kuala Lumpur pagerange: 831-835 refereed: TRUE isbn: 9781457719677 citation: Anggraeni, S. and Hussin, F.A. and Jeoti, V. (2012) Pipelined architecture for low density parity check encoder. In: UNSPECIFIED.