TY  - CONF
SN  - 9781457719677
N2  - This paper proposes a pipelined architecture for low density parity check encoder by pipelining information bits and sub-matrices of parity check matrix (H) using two bit-wise operations. The two bit-wise operations are multiplication and exclusive-OR. The investigation is done by exploring two methods of pipelining using the two bit-wise operations in the proposed architecture. The first method of pipelining uses combination of shift register and memory for the sub-matrices of H while the second method of pipelining uses shift register for the information bits and the sub-matrices of H. It is shown that the second method of pipelining increases the throughput but has the largest units of shift registers and flip-flops in the design. © 2011 IEEE.
KW  - encoder; Exclusive-OR; Information bit; Low density parity check; Parity check matrices; Pipelined architecture; Proposed architectures; Sub-matrices
KW  -  Architecture; Matrix algebra; Pipe linings; Shift registers
KW  -  Pipeline processing systems
TI  - Pipelined architecture for low density parity check encoder
Y1  - 2012///
ID  - scholars2700
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-84867972450&doi=10.1109%2fICIAS.2012.6306129&partnerID=40&md5=da61cebc4d9584bfe8e99e2ed02dd9a9
A1  - Anggraeni, S.
A1  - Hussin, F.A.
A1  - Jeoti, V.
N1  - cited By 0; Conference of 2012 4th International Conference on Intelligent and Advanced Systems, ICIAS 2012 ; Conference Date: 12 June 2012 Through 14 June 2012; Conference Code:93534
CY  - Kuala Lumpur
EP  - 835
SP  - 831
AV  - none
VL  - 2
ER  -