<> "The repository administrator has not yet configured an RDF license."^^ . <> . . . "Pipelined architecture for low density parity check encoder"^^ . "This paper proposes a pipelined architecture for low density parity check encoder by pipelining information bits and sub-matrices of parity check matrix (H) using two bit-wise operations. The two bit-wise operations are multiplication and exclusive-OR. The investigation is done by exploring two methods of pipelining using the two bit-wise operations in the proposed architecture. The first method of pipelining uses combination of shift register and memory for the sub-matrices of H while the second method of pipelining uses shift register for the information bits and the sub-matrices of H. It is shown that the second method of pipelining increases the throughput but has the largest units of shift registers and flip-flops in the design. © 2011 IEEE."^^ . "2012" . . "2" . . "ICIAS 2012 - 2012 4th International Conference on Intelligent and Advanced Systems: A Conference of World Engineering, Science and Technology Congress (ESTCON) - Conference Proceedings"^^ . . . . . . . . . . . . . . "S."^^ . "Anggraeni"^^ . "S. Anggraeni"^^ . . "V."^^ . "Jeoti"^^ . "V. Jeoti"^^ . . "F.A."^^ . "Hussin"^^ . "F.A. Hussin"^^ . . . . . "HTML Summary of #2700 \n\nPipelined architecture for low density parity check encoder\n\n" . "text/html" . .