%0 Conference Paper
%A Anggraeni, S.
%A Hussin, F.A.
%A Jeoti, V.
%D 2012
%F scholars:2700
%K encoder; Exclusive-OR; Information bit; Low density parity check; Parity check matrices; Pipelined architecture; Proposed architectures; Sub-matrices, Architecture; Matrix algebra; Pipe linings; Shift registers, Pipeline processing systems
%P 831-835
%R 10.1109/ICIAS.2012.6306129
%T Pipelined architecture for low density parity check encoder
%U https://khub.utp.edu.my/scholars/2700/
%V 2
%X This paper proposes a pipelined architecture for low density parity check encoder by pipelining information bits and sub-matrices of parity check matrix (H) using two bit-wise operations. The two bit-wise operations are multiplication and exclusive-OR. The investigation is done by exploring two methods of pipelining using the two bit-wise operations in the proposed architecture. The first method of pipelining uses combination of shift register and memory for the sub-matrices of H while the second method of pipelining uses shift register for the information bits and the sub-matrices of H. It is shown that the second method of pipelining increases the throughput but has the largest units of shift registers and flip-flops in the design. © 2011 IEEE.
%Z cited By 0; Conference of 2012 4th International Conference on Intelligent and Advanced Systems, ICIAS 2012 ; Conference Date: 12 June 2012 Through 14 June 2012; Conference Code:93534