relation: https://khub.utp.edu.my/scholars/2700/
title: Pipelined architecture for low density parity check encoder
creator: Anggraeni, S.
creator: Hussin, F.A.
creator: Jeoti, V.
description: This paper proposes a pipelined architecture for low density parity check encoder by pipelining information bits and sub-matrices of parity check matrix (H) using two bit-wise operations. The two bit-wise operations are multiplication and exclusive-OR. The investigation is done by exploring two methods of pipelining using the two bit-wise operations in the proposed architecture. The first method of pipelining uses combination of shift register and memory for the sub-matrices of H while the second method of pipelining uses shift register for the information bits and the sub-matrices of H. It is shown that the second method of pipelining increases the throughput but has the largest units of shift registers and flip-flops in the design. © 2011 IEEE.
date: 2012
type: Conference or Workshop Item
type: PeerReviewed
identifier:   Anggraeni, S. and Hussin, F.A. and Jeoti, V.  (2012) Pipelined architecture for low density parity check encoder.  In: UNSPECIFIED.     
relation: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84867972450&doi=10.1109%2fICIAS.2012.6306129&partnerID=40&md5=da61cebc4d9584bfe8e99e2ed02dd9a9
relation: 10.1109/ICIAS.2012.6306129
identifier: 10.1109/ICIAS.2012.6306129