@inproceedings{scholars222,
            year = {2007},
             doi = {10.1109/WOCN.2007.4284135},
            note = {cited By 0; Conference of 4th IEEE and IFIP International Conference on Wireless and Optical Communications Networks, WOCN 2007 ; Conference Date: 2 July 2007 Through 4 July 2007; Conference Code:73243},
         journal = {4th IEEE and IFIP International Conference on Wireless and Optical Communications Networks, WOCN 2007},
         address = {Singapore},
           title = {Hardware reduction in optical parallel interference cancellation},
          author = {Elfadel, N. and Aziz, A. A. and Idriss, E. and Mohammed, A. and Saad, N. M.},
            isbn = {1424410045; 9781424410040},
        keywords = {Bit error rate; Chlorine compounds; Code division multiple access; Codes (symbols); Communication systems; Computer networks; Multiple access interference; Photonics; Probability; Radio interference; Risk assessment; Signal interference, Hardware complexities; International conferences; Processing Time, Optical communication},
             url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-50449085297&doi=10.1109\%2fWOCN.2007.4284135&partnerID=40&md5=5aed0a46012fece4be562f283aba09c0},
        abstract = {The success of parallel interference cancellation (PIC) to reduce the multiple access interference in the wireless CDMA communication systems has motivated the communication community to investigate the potential of PIC in the optical CDMA domain. However, the usage of PIC in optical domain will increase the demand for hardware complexity which results in higher processing time and cost. The hardware complexity increases in the receiver side of Optical PIC (OPIC) when the number of transmitter (users) increases. To overcome these difficulties, we propose a simple and efficient technique based mainly on the OPIC and referred as One Stage OPIC (OS-OPIC). Optical Orthogonal Code (OOC) is adopted as a signature sequence for the performance analysis and a new expression for the error probability is derived. The results show that the proposed method is effective to reduce the hardware complexity, processing time and cost while maintaining the same bit error probability at the cost of increasing the threshold value. {\^A}{\copyright}2007 IEEE.}
}