TY  - JOUR
KW  - Authentication; Field programmable gate arrays (FPGA); Hash functions; Parallel architectures; Authenticated encryption; Authenticated encryption with associated data; CUDA; GPU implementation; High-throughput; Lightweight authenticated encryption; National Institute of Standards and Technology; Graphics processing unit
A1  - Chan, Jia Lin
A1  - Lee, Wai Kong
A1  - Wong, Denis Chee Keong
A1  - Yap, W. S.
A1  - Ooi, Boonyaik Yaik
A1  - Goi, Bok Min
ID  - scholars20419
VL  - 27
PB  - Springer
TI  - High throughput acceleration of NIST lightweight authenticated encryption schemes on GPU platform
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-85193493487&doi=10.1007%2Fs10586-024-04463-x&partnerID=40&md5=00573e2aec8dffa979f874993ff07611
JF  - Cluster Computing
N2  - Authenticated encryption with associated data (AEAD) has become prominent over time because it offers authenticity and confidentiality simultaneously. In 2018, the National Institute of Standards and Technology (NIST) initiated a competition to standardize lightweight AEAD and hash functions, with Ascon as the final winner among the 10 finalists. Numerous prior works evaluated their performance on FPGA and ASIC, but not on a parallel architecture like GPU, which is a common accelerator already found in many existing cloud servers. In this work, the first GPU implementation of the NIST AEAD finalists is proposed. Several GPU implementation techniques applicable to all AEAD schemes are presented, along with novel techniques for some specific schemes to enhance throughput performance. Experimental results show that all NIST AEAD finalists can achieve high throughput (up to 111.53M AEAD per second), approximately 142.19 and 72.65 improvement compared to unoptimized GPU version, and the investigated FPGA results respectively. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024.
SP  - 11213 
SN  - 13867857
AV  - none
EP  -  11235
N1  - Cited by: 0
Y1  - 2024///
IS  - 8
ER  -