TY  - CONF
CY  - Kuala Lumpur
AV  - none
N2  - The objective of this paper was to develop a real time hardware image processing system which is based on Field Programmable Gate Array (FPGA). The chosen image processing algorithms implemented was edge detection. This work utilizes Altera DE2 development board powered by Cyclone II FGPA pair with 1.3 Mega pixel CMOS camera from Terasic Technologies. Verilog HDL was used as the hardware programming language for a real-time edge detection system. The resulting edge detection images showed that a simple edge detection algorithm was implemented on Cyclone II FPGA for real-time image processing. ©2007 IEEE.
N1  - cited By 7; Conference of 2007 International Conference on Intelligent and Advanced Systems, ICIAS 2007 ; Conference Date: 25 November 2007 Through 28 November 2007; Conference Code:74506
TI  - Implementation of real-time simple edge detection on FPGA
ID  - scholars184
SP  - 1404
KW  - Computer hardware description languages; Computer programming languages; Digital image storage; Field programmable gate arrays (FPGA); Image processing; Imaging systems; Logic gates; Optical sensors
KW  -  CMOS cameras; Detection systems; Edge Detection algorithms; Image processing algorithms; Mega pixels; Processing systems; Programming languages; Real times; Verilog HDL
KW  -  Edge detection
Y1  - 2007///
SN  - 1424413559; 9781424413553
A1  - Shukor, M.N.B.M.
A1  - Lo, H.H.
A1  - Sebastian, P.
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-57949093012&doi=10.1109%2fICIAS.2007.4658616&partnerID=40&md5=a3834edf1cae56b38ab3eda73b1fb892
EP  - 1406
ER  -