eprintid: 1806
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/18/06
datestamp: 2023-11-09 15:49:58
lastmod: 2023-11-09 15:49:58
status_changed: 2023-11-09 15:41:23
type: conference_item
metadata_visibility: show
creators_name: Abdul Latif, M.A.
creators_name: Zain Ali, N.B.
creators_name: Hussin, F.A.
title: A case study of process-variation effect to SoC analog circuits
ispublished: pub
keywords: Analog; Analog applications; Circuit blocks; Circuit performance; Circuit reliability; diff-amp; Key process; Match devices; Negative bias temperature instability; Process Variation; Reliability sensitivity; Submicron process technology; System-on-chip applications, Aging of materials; Application specific integrated circuits; Bias voltage; Computational complexity; Differential amplifiers; Digital circuits; Electric network analysis; Field effect transistors; Negative temperature coefficient; Programmable logic controllers; Reliability; Thermodynamic stability, Analog circuits
note: cited By 2; Conference of 2011 IEEE Recent Advances in Intelligent Computational Systems, RAICS 2011 ; Conference Date: 22 September 2011 Through 24 September 2011; Conference Code:87395
abstract: Recent submicron process technology scaling leads the urgency to build an efficient methodology of characterizing and modeling the process variation effect, for example, the threshold voltage, Vt. This is one of the key process parameters that must be extensively modeled and validated for accurate circuit performance. Furthermore, this requirement is even much more critical for analog applications which demand an ability to match devices precisely. Analog circuits use larger device dimensions as compared to digital circuits in order to minimize the process variation implication. This has led Negative Bias Temperature Instability (NBTI) to be the most performance limiter compared to the rest of reliability mechanisms. This reliability sensitivity is even more challenging as most of the circuit blocks (digital and analog) are fabricated on the same chip for system-on-chip (SoC) applications. This paper will describe in detail the actions taken to minimize impact to customers and will show how important proper aging simulations to be conducted with the right combination of process, voltage, temperature (PVT) and coupling/timing to occur due to process variation effect beyond specifications on analog differential amplifier (diffamp) circuits in SoC products. © 2011 IEEE.
date: 2011
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-81355150505&doi=10.1109%2fRAICS.2011.6069366&partnerID=40&md5=97775d636ac9d8b8aa9e62c3d6ef90f1
id_number: 10.1109/RAICS.2011.6069366
full_text_status: none
publication: 2011 IEEE Recent Advances in Intelligent Computational Systems, RAICS 2011
place_of_pub: Trivandrum, Kerala
pagerange: 520-523
refereed: TRUE
isbn: 9781424494774
citation:   Abdul Latif, M.A. and Zain Ali, N.B. and Hussin, F.A.  (2011) A case study of process-variation effect to SoC analog circuits.  In: UNSPECIFIED.