@inproceedings{scholars1781,
         address = {Kuala Lumpur},
           title = {NBTI-induced 8-Bit DAC circuit mismatch in System-On-Chip (SoC)},
         journal = {Proceedings of the 3rd Asia Symposium on Quality Electronic Design, ASQED 2011},
           pages = {29--36},
            note = {cited By 1; Conference of 3rd Asia Symposium on Quality Electronic Design, ASQED 2011 ; Conference Date: 19 July 2011 Through 20 July 2011; Conference Code:88117},
             doi = {10.1109/ASQED.2011.6111698},
            year = {2011},
            isbn = {9781457701443},
          author = {Latif, M. A. A. and Ali, N. B. Z. and Hussin, F. A.},
        abstract = {This paper focuses on Negative Bias Temperature Instability (NBTI) awareness to the circuit designer for reliable design of the System-On-a-Chip (SoC) analog circuit. The reliability performance of all matched pair such as current source and differential pair circuits, such as Bandgap Reference, is at the mercy of aging differential. Aging simulation (AgingSim) is mandatory to obtain realistic risk evaluation for circuit design reliability qualification. It is applicable to all circuit aging problems covering both analog and digital. Failure rate varies as a function of voltage and temperature. It is shown that PMOS is the reliability-critical device and NBTI is the most critical failure mechanism for analog circuit performance in sub-micrometer CMOS technology. This paper provides a complete reliability simulation analysis of an 8 bit Cathode-Ray-Tube (CRT) Digital-Analog-Converter (DAC) under 90nm process technology and analyze the effect of NBTI using aging simulation tool. A Burn-In experiment was performed to review the reliability sensitivity of the DAC design. {\^A}{\copyright} 2011 IEEE.},
        keywords = {Analog converters; Bandgap Reference; Burn-in; Circuit aging; Circuit designers; Circuit designs; Circuit mismatch; Circuit performance; Circuit reliability; CMOS technology; Critical failures; Current sources; Differential pairs; Failure rate; Negative bias temperature instability; Process Technologies; Reliability performance; Reliability sensitivity; Reliability simulation; Risk evaluation; Simulation tool; Submicrometers; System-on-a-chip; System-On-Chip, Aging of materials; Application specific integrated circuits; Cathode ray tubes; CMOS integrated circuits; Design; Field effect transistors; Integrated circuit manufacture; Microprocessor chips; Negative temperature coefficient; Program processors; Programmable logic controllers; Reliability analysis; Thermodynamic stability, Analog circuits},
             url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-84855907379&doi=10.1109\%2fASQED.2011.6111698&partnerID=40&md5=ce8c5916cfda329ed48adbfcd81ee836}
}