%J IEEE Region 10 Annual International Conference, Proceedings/TENCON
%L scholars1763
%O cited By 7; Conference of 2011 IEEE Region 10 Conference: Trends and Development in Converging Technology Towards 2020, TENCON 2011 ; Conference Date: 21 November 2011 Through 24 November 2011; Conference Code:88417
%R 10.1109/TENCON.2011.6129200
%D 2011
%K Bandwidth constraint; Camera systems; Clock cycles; Clock frequency; depth-map; disparity algorithm; Frames per seconds; Hardware architecture; Logic elements; Mega-pixel; Memory controller; Parallel processing; Processing speed; Processing systems; Processor architectures; Resource consumption; Resource usage; Sum of absolute differences; Window Size, Algorithms; Architecture; Computer architecture; Field programmable gate arrays (FPGA); Pixels, Image matching
%X Depth-map algorithm allows camera system to estimate depth. It is a computational intensive algorithm, but can be implemented with high speed on hardware due to the parallelism property. When depth-map algorithm is implemented on FPGA, resource consumption is one of the issues. The problem is normally resolved by modifying the algorithm, but the problem can also be solved by implementing new hardware architectures without modification of the depth-map algorithm. This work implemented five different processor architectures for the sum of absolute difference (SAD) depth-map algorithm on FPGA in real-time. Resource usage and performance of these architectures were compared. Memory contention and bandwidth constraints were resolved by using self-initiative memory controller, FIFOs and line buffers. Parallel processing was utilized to achieve high processing speed at low clock frequency. Memory-based line buffers were used instead of register-based line buffers to save 62.4 of logic elements (LEs) used. Usage of registers to replace repetitive subtractors saves 24.75 of LEs. The system achieves performance of 295 mega pixel disparity per second(MPDS) for the architecture with 640x480 pixels image, 3x3 pixels window size, 32 pixels disparity range and 30 frames per second. It achieves processing speed of 590 MPDS for the 64 pixels disparity range architecture. The disparity matching module works at the frequency of 10 MHz and produces one pixel of result every clock cycle. © 2011 IEEE.
%P 706-710
%A N.H. Tan
%A N.H. Hamid
%A P. Sebastian
%A Y.V. Voon
%T Resource minimization in a real-time depth-map processing system on FPGA
%C Bali