TY  - CONF
AV  - none
TI  - An Adaptive Hardware Architecture using Quantized HOG Features for Object Detection
ID  - scholars17374
SP  - 113
KW  - Feature extraction; Graphic methods; Memory architecture; Object detection; Object recognition; Pipeline processing systems; Static random access storage
KW  -  Hardware architecture; Histogram of oriented gradient features; Histogram of oriented gradients; Memory footprint; Objects detection; Performance; Quantized histograms; Support vectors machine; Supported vector machines
KW  -  Support vector machines
N2  - This article presents an adaptive hardware architecture for high-performance object detection using Histogram of Oriented Gradient (HOG) features in combination with Supported Vector Machines (SVM). This architecture can adapt to various bit-width representations of HOG features by using the quantization technique. The HOG features can be represented from 8 bits to 4 bits to remove the bubble in the processing pipeline and reduce the memory footprint. As a result, the overall throughput is robustly increased as the number of bits decreases. Moreover, we propose a new cell-reused strategy to speed up the system throughput and reduce memory footprint. The proposed architecture has been implemented in TSMC 65nm technology with a maximum operating frequency of 500MHz and throughput of 3.98Gbps. The total hardware area cost is about 167KGEs and 212kb SRAMs. © 2022 IEEE.
N1  - cited By 2; Conference of 2022 IEEE International Conference on IC Design and Technology, ICICDT 2022 ; Conference Date: 21 September 2022 Through 23 September 2022; Conference Code:184070
PB  - Institute of Electrical and Electronics Engineers Inc.
SN  - 9781665459013
Y1  - 2022///
EP  - 116
A1  - Nguyen, N.-D.
A1  - Bui, D.-H.
A1  - Hussin, F.A.
A1  - Tran, X.-T.
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-85142756779&doi=10.1109%2fICICDT56182.2022.9933068&partnerID=40&md5=8dbc6c28f9905b2df68cc139546542d7
ER  -