%0 Conference Paper
%A Nguyen, N.-D.
%A Bui, D.-H.
%A Hussin, F.A.
%A Tran, X.-T.
%D 2022
%F scholars:17374
%I Institute of Electrical and Electronics Engineers Inc.
%K Feature extraction; Graphic methods; Memory architecture; Object detection; Object recognition; Pipeline processing systems; Static random access storage, Hardware architecture; Histogram of oriented gradient features; Histogram of oriented gradients; Memory footprint; Objects detection; Performance; Quantized histograms; Support vectors machine; Supported vector machines, Support vector machines
%P 113-116
%R 10.1109/ICICDT56182.2022.9933068
%T An Adaptive Hardware Architecture using Quantized HOG Features for Object Detection
%U https://khub.utp.edu.my/scholars/17374/
%X This article presents an adaptive hardware architecture for high-performance object detection using Histogram of Oriented Gradient (HOG) features in combination with Supported Vector Machines (SVM). This architecture can adapt to various bit-width representations of HOG features by using the quantization technique. The HOG features can be represented from 8 bits to 4 bits to remove the bubble in the processing pipeline and reduce the memory footprint. As a result, the overall throughput is robustly increased as the number of bits decreases. Moreover, we propose a new cell-reused strategy to speed up the system throughput and reduce memory footprint. The proposed architecture has been implemented in TSMC 65nm technology with a maximum operating frequency of 500MHz and throughput of 3.98Gbps. The total hardware area cost is about 167KGEs and 212kb SRAMs. © 2022 IEEE.
%Z cited By 2; Conference of 2022 IEEE International Conference on IC Design and Technology, ICICDT 2022 ; Conference Date: 21 September 2022 Through 23 September 2022; Conference Code:184070