TY  - CONF
ID  - scholars17346
N2  - In this paper, a modified single-phase 63-level asymmetric multi-level inverter (MLI) topology is proposed to reduce THD. The sinusoidally modulated staircase switching technique is utilized to control level generating circuitry to produce only positive voltage across H-Bridge terminals. H-Bridge circuitry is used to generate polarities. In this technique, optimal switch count is considered for this topology. The proposed topology was analyzed in MATLAB/SIMULINK and also a mathematical analysis was done for THD calculation. In both analyses, the THD was found 0.27 for the modified topology. For experimental validation of this modified topology, a prototype was developed and tested in the laboratory. The experimental waveform for a 60W electric bulb is shown in this paper. Finally, The THD of output voltage and efficiency of the inverter were found 1.13 and 93.7 respectively using HIOKI PW3337 POWER METER. © 2022 IEEE.
EP  - 6
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-85143444832&doi=10.1109%2fIEACon55029.2022.9951803&partnerID=40&md5=897a7ba1e7a0ceaf14cd1c6a449e2e9c
SN  - 9781665480062
PB  - Institute of Electrical and Electronics Engineers Inc.
SP  - 1
A1  - Rafiul Islam, M.
A1  - Mahmudul Hasan, M.
A1  - Kannan, R.
KW  - Bridge circuits; DC-DC converters; Electric inverters
KW  -  63 level inverte; H-bridges; Inverter topologies; MOS-FET; MOSFETs; Multi Level Inverter (MLI); Multilevels; Single phasis; Switching techniques; THD
KW  -  Topology
TI  - Development of a Modified 63-Level Asymmetric Multi-Level Inverter to Minimize THD
Y1  - 2022///
AV  - none
N1  - cited By 1; Conference of 3rd IEEE Industrial Electronics and Applications Conference, IEACon 2022 ; Conference Date: 3 October 2022 Through 4 October 2022; Conference Code:184531
ER  -