%0 Conference Paper
%A Rafiul Islam, M.
%A Mahmudul Hasan, M.
%A Kannan, R.
%D 2022
%F scholars:17346
%I Institute of Electrical and Electronics Engineers Inc.
%K Bridge circuits; DC-DC converters; Electric inverters, 63 level inverte; H-bridges; Inverter topologies; MOS-FET; MOSFETs; Multi Level Inverter (MLI); Multilevels; Single phasis; Switching techniques; THD, Topology
%P 1-6
%R 10.1109/IEACon55029.2022.9951803
%T Development of a Modified 63-Level Asymmetric Multi-Level Inverter to Minimize THD
%U https://khub.utp.edu.my/scholars/17346/
%X In this paper, a modified single-phase 63-level asymmetric multi-level inverter (MLI) topology is proposed to reduce THD. The sinusoidally modulated staircase switching technique is utilized to control level generating circuitry to produce only positive voltage across H-Bridge terminals. H-Bridge circuitry is used to generate polarities. In this technique, optimal switch count is considered for this topology. The proposed topology was analyzed in MATLAB/SIMULINK and also a mathematical analysis was done for THD calculation. In both analyses, the THD was found 0.27 for the modified topology. For experimental validation of this modified topology, a prototype was developed and tested in the laboratory. The experimental waveform for a 60W electric bulb is shown in this paper. Finally, The THD of output voltage and efficiency of the inverter were found 1.13 and 93.7 respectively using HIOKI PW3337 POWER METER. © 2022 IEEE.
%Z cited By 1; Conference of 3rd IEEE Industrial Electronics and Applications Conference, IEACon 2022 ; Conference Date: 3 October 2022 Through 4 October 2022; Conference Code:184531