eprintid: 1677
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/16/77
datestamp: 2023-11-09 15:49:50
lastmod: 2023-11-09 15:49:50
status_changed: 2023-11-09 15:41:07
type: conference_item
metadata_visibility: show
creators_name: Anggraeni, S.
creators_name: Hussin, F.A.
creators_name: Jeoti, V.
title: High rate (3, k) regular LDPC encoder architecture
ispublished: pub
keywords: Code length; Code rates; encoder; Encoder architecture; encoding complexity; Encoding methods; High rate; LDPC codes; Low density parity check; Parity check matrices, Encoding (symbols); Field programmable gate arrays (FPGA); Matrix algebra; Sustainable development, Error correction
note: cited By 0; Conference of 3rd National Postgraduate Conference - Energy and Sustainability: Exploring the Innovative Minds, NPC 2011 ; Conference Date: 19 September 2011 Through 20 September 2011; Conference Code:88531
abstract: This paper highlights recent developments in low density parity check (LDPC) encoder. There are some parameters applied in LDPC encoder such as type of LDPC codes, code length, code rate and encoding method. We emphasize that no attempts have been made for the implementation of (3, k) regular LDPC encoder with high code rate (R 0.875) and few works on flexible LDPC encoder which accommodates various code rates and code lengths. Therefore, this paper proposes a high rate (3, k) regular LDPC encoder architecture which is suitable for high code rate (R 0.875) applications. Division of workloads between stages is built based on the number of non-zero elements in the parity check matrix (H). © 2011 IEEE.
date: 2011
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84857077771&doi=10.1109%2fNatPC.2011.6136390&partnerID=40&md5=ada06b2faf4a7990bad97402fc997a75
id_number: 10.1109/NatPC.2011.6136390
full_text_status: none
publication: 2011 National Postgraduate Conference - Energy and Sustainability: Exploring the Innovative Minds, NPC 2011
place_of_pub: Perak
refereed: TRUE
isbn: 9781457718847
citation:   Anggraeni, S. and Hussin, F.A. and Jeoti, V.  (2011) High rate (3, k) regular LDPC encoder architecture.  In: UNSPECIFIED.