@inproceedings{scholars167,
            note = {cited By 0; Conference of 2007 International Conference on Intelligent and Advanced Systems, ICIAS 2007 ; Conference Date: 25 November 2007 Through 28 November 2007; Conference Code:74506},
         address = {Kuala Lumpur},
           title = {Design of voltage controlled oscillator (VCO) for ultra wideband (UWB) CMOS frequency synthesizer},
             doi = {10.1109/ICIAS.2007.4658611},
           pages = {1383--1386},
         journal = {2007 International Conference on Intelligent and Advanced Systems, ICIAS 2007},
            year = {2007},
          author = {Zafar, S. and Zulkifli, T. Z. A. and Awan, M.},
        keywords = {Channel capacity; Communication channels (information theory); Frequency allocation; Frequency division multiple access; Frequency synthesizers; Multiplexing; Orthogonal frequency division multiplexing; Phase noise; Signal generators; Telecommunication systems; Varactors; Variable frequency oscillators; Wireless telecommunication systems, CMOS; Current consumptions; Damping resistances; Fundamental building blocks; Gate structures; Multi band orthogonal frequency division multiplexing (MB-OFDM); Process Technologies; Supply voltages; Synthesizer architectures; Tuning ranges; Ultra wideband (UWB); VCO circuits; Voltage controlled oscillator (VCO), Frequency division multiplexing},
            isbn = {1424413559; 9781424413553},
             url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-57949104618&doi=10.1109\%2fICIAS.2007.4658611&partnerID=40&md5=5409c11bff7ecdf359bb2dd93e071c56},
        abstract = {Voltage controlled oscillator is one of the fundamental building blocks in the frequency synthesizer architecture. A 4.224-GHz CMOS complementary cross-coupled LC-VCO is designed for multi-band OFDM (MB-OFDM) ultra-wideband (UWB) application. The tuning range of the VCO is from 3.77-GHz to 4.27-GHz or 12-, which was achieved through pMOS based varactors. The VCO core current consumption is 1.9-mA from a 1.8-V supply voltage. With the combination of source damping resistance of 40-{\^I}{\copyright}, multi-finger gate structure of pMOS based varactors the 2-{\^I}1/4m x 284 fingers and tail biasing resistance of 232-{\^I}{\copyright}, the phase noise were simulated at - 94.7-dBc/Hz and -120.1-dBc/Hz at 100-kHz and 1-MHz offset, respectively. The VCO circuit is designed in Silterra 0.18-{\^I}1/4m 1-poly 6-metal RFMOS process technology. {\^A}{\copyright}2007 IEEE.}
}