eprintid: 1599
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/00/15/99
datestamp: 2023-11-09 15:49:46
lastmod: 2023-11-09 15:49:46
status_changed: 2023-11-09 15:40:57
type: conference_item
metadata_visibility: show
creators_name: Alser, M.H.
creators_name: Assaad, M.M.
title: Design and modeling of low-power clockless serial link for data communication systems
ispublished: pub
keywords: CDR; Design and modeling; High speed communication networks; High-speed; Integrated circuit technology; Inter-module; Low Power; Multi-bits; On chips; Processing speed; Quarter-rate; SerDes; Serial link; Synchronous communications; System on chips, Application specific integrated circuits; Data communication systems; Integrated circuits; Microprocessor chips; Phase locked loops, Sustainable development
note: cited By 4; Conference of 3rd National Postgraduate Conference - Energy and Sustainability: Exploring the Innovative Minds, NPC 2011 ; Conference Date: 19 September 2011 Through 20 September 2011; Conference Code:88531
abstract: Due to the continuing progress in integrated circuit technology, SoC (system-on-chip) is becoming larger requiring many long on-chip wires that interconnect SoC's modules. However, it is becoming increasingly challenging to synchronously and reliably communicate synchronous data between high-speed modules. Therefore, to take advantage of the increased module's processing speed available and to improve the overall system performance requires high-speed communication networks. This paper overviews the problems and limitations associated with the use of multi-bit conventional bus as a medium of synchronous communication in today's multi-module based SoC and presents an asynchronous serial link as a potential high-performance alternative solution. Furthermore, it reviews the current state-of-the-art of serial links and proposes a new architecture based on quarter-rate concept that will eventually lead to the implementation of a low-power and high-speed intermodule link in SoC. © 2011 IEEE.
date: 2011
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84857094684&doi=10.1109%2fNatPC.2011.6136441&partnerID=40&md5=b4bf5290cfd83993f25776ac0d792f5c
id_number: 10.1109/NatPC.2011.6136441
full_text_status: none
publication: 2011 National Postgraduate Conference - Energy and Sustainability: Exploring the Innovative Minds, NPC 2011
place_of_pub: Perak
refereed: TRUE
isbn: 9781457718847
citation:   Alser, M.H. and Assaad, M.M.  (2011) Design and modeling of low-power clockless serial link for data communication systems.  In: UNSPECIFIED.