%0 Conference Paper
%A Alser, M.H.
%A Assaad, M.M.
%D 2011
%F scholars:1599
%K CDR; Design and modeling; High speed communication networks; High-speed; Integrated circuit technology; Inter-module; Low Power; Multi-bits; On chips; Processing speed; Quarter-rate; SerDes; Serial link; Synchronous communications; System on chips, Application specific integrated circuits; Data communication systems; Integrated circuits; Microprocessor chips; Phase locked loops, Sustainable development
%R 10.1109/NatPC.2011.6136441
%T Design and modeling of low-power clockless serial link for data communication systems
%U https://khub.utp.edu.my/scholars/1599/
%X Due to the continuing progress in integrated circuit technology, SoC (system-on-chip) is becoming larger requiring many long on-chip wires that interconnect SoC's modules. However, it is becoming increasingly challenging to synchronously and reliably communicate synchronous data between high-speed modules. Therefore, to take advantage of the increased module's processing speed available and to improve the overall system performance requires high-speed communication networks. This paper overviews the problems and limitations associated with the use of multi-bit conventional bus as a medium of synchronous communication in today's multi-module based SoC and presents an asynchronous serial link as a potential high-performance alternative solution. Furthermore, it reviews the current state-of-the-art of serial links and proposes a new architecture based on quarter-rate concept that will eventually lead to the implementation of a low-power and high-speed intermodule link in SoC. © 2011 IEEE.
%Z cited By 4; Conference of 3rd National Postgraduate Conference - Energy and Sustainability: Exploring the Innovative Minds, NPC 2011 ; Conference Date: 19 September 2011 Through 20 September 2011; Conference Code:88531