TY  - JOUR
AV  - none
TI  - An Efficient VLSI Architecture for FastICA by Using the Algebraic Jacobi Method for EVD
SP  - 58287
N1  - cited By 7
PB  - Institute of Electrical and Electronics Engineers Inc.
SN  - 21693536
EP  - 58305
ID  - scholars15804
KW  - Eigenvalues and eigenfunctions; Field programmable gate arrays (FPGA); Independent component analysis; Newton-Raphson method; Polynomial approximation; Portable equipment; Reusability; VLSI circuits
KW  -  Complex analysis; Computation speed; Eigenvalue decomposition; Hardware implementations; Hardware platform; Independent components analysis; Off-line analysis; VLSI architectures
KW  -  Blind source separation
N2  - Blind source separation (BSS) is a problem that appears in many research fields. Fast Independent components analysis (FastICA) is one of the techniques to solve the problem. The researchers have verified the effectiveness of the technique through the offline analysis of the public datasets. The development of a real-time portable system involving such a computationally complex analysis requires an efficient hardware implementation of FastICA. A Field programmable gate array (FPGA) and an application-specific integrated circuit (ASIC) are two promising hardware platforms to implement FastICA. This work proposes a new method, called ALgebraic Jacobi Method (ALJM), for performing eigenvalue decomposition (EVD) required for the implementation of FastICA. We use a simplification, a polynomial approximation, and the Newton-Raphson method for calculating the Jacobi rotation. In this way, we ensure hardware reusability between the EVD stage and the weight vector estimation (WVE) stage of FastICA which reduces the computational complexity and the power consumption, without compromising its computation speed. We evaluate the ALJM-based FastICA by performing BSS on the linear mixtures of the deterministic and the random signals and comparing the performance results with the existing methods. After verifying its functionality and numerical stability, we propose a scalable systolic processing array (SPA) for the ALJM-based FastICA and implement it on Spartan-6 FPGA. By comparing the existing implementations of FastICA, in terms of speed, area, and power, we conclude that the ALJM-based FastICA is one of the most efficient methods for prototyping and commercializing a real-time portable system comprising FastICA. © 2013 IEEE.
Y1  - 2021///
VL  - 9
JF  - IEEE Access
A1  - Sajjad, M.
A1  - Yusoff, M.Z.
A1  - Yahya, N.
A1  - Haider, A.S.
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-85104244059&doi=10.1109%2fACCESS.2021.3072495&partnerID=40&md5=e1e552a53599baf56ee2a345704b4fb8
ER  -