TY  - JOUR
KW  - Cutoff frequency; Delay circuits; Electric inverters; Electric power supplies to apparatus; Ions; Schottky barrier diodes; Silicon on insulator technology; Transconductance; Tunnels
KW  -  Cut-off frequency (fT); Figures of merits; Gain frequencies; Gain-bandwidth products; Low-power design; Oscillation frequency; Schottky barriers; Short-channel effect
KW  -  MOSFET devices
ID  - scholars15743
N2  - In this work, a new structure of Schottky tunneling MOSFET has been designed and simulated. The proposed device structure uses floating gates and dual material main gates to counter short channel effects and to improve RF/Analog figures of merit for low power design applications. The use of floating gates modulates the Schottky barrier width, hence improves the ON state and RF/Analog figures of merit performance of the proposed device in comparison to a conventional device. A significantly high ION(1.231 � 10-4A μm) and ION/IOFF ratio (2.52 � 105) is achieved in the proposed ST-MOSFET in comparison to conventional ST-MOSFET having ION (1 � 10-7A μm) and ION/IOFF ratio (1 � 102). It has been observed that there is more than 100 times improvement in cutoff frequency (fT), transconductance frequency product (TFP), gain frequency product (GFP), gain transconductance frequency product (GTFP), gain bandwidth product (GBP) and max oscillation frequency (fmax) in comparison to conventional ST-MOSFET. In addition, there are reductions of 98 and 33.33 in switching ON and OFF delays respectively in the proposed device-based inverter circuit in comparison to conventional ST-MOSFET based inverter circuit. Furthermore, the proposed ST-MOSFET device does not require any highly doped regions, hence does not have any doping related issues. © 2013 IEEE.
VL  - 9
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-85107173607&doi=10.1109%2fACCESS.2021.3083929&partnerID=40&md5=98214f16a9e85119155db7540b324640
JF  - IEEE Access
A1  - Rashid, S.
A1  - Bashir, F.
A1  - Khanday, F.A.
A1  - Rafiq Beigh, M.
A1  - Hussin, F.A.
Y1  - 2021///
SP  - 80158
TI  - 2-D Design of Double Gate Schottky Tunnel MOSFET for High-Performance Use in Analog/RF Applications
N1  - cited By 15
AV  - none
EP  - 80169
SN  - 21693536
PB  - Institute of Electrical and Electronics Engineers Inc.
ER  -