%P 835-839
%I Institute of Electrical and Electronics Engineers Inc.
%A H. Syed
%A F.A. Khanday
%A F. Zahoor
%A F.A. Hussin
%T Performance Analysis of CNTFET-ReRAM based Crossbar Network for In-Memory Computing
%L scholars14561
%J 2021 6th International Conference on Recent Trends on Electronics, Information, Communication and Technology, RTEICT 2021
%O cited By 1; Conference of 6th International Conference on Recent Trends on Electronics, Information, Communication and Technology, RTEICT 2021 ; Conference Date: 27 August 2021 Through 28 August 2021; Conference Code:173266
%R 10.1109/RTEICT52294.2021.9573900
%D 2021
%X With scaling of transistors reaching its physical limits, the end of Moores law is imminent. The prevalent CMOS technologies are facing severe design issues like short channel effects, lithographic limitations etc in undergoing further scaling. Also the huge advancements made in processing technologies have made the effects of memory wall more prominent. Because of the growing divide between processing time and time taken to transfer data, the severity of Von Neumann bottleneck is being felt more than ever. Thus there is an emergent need to shift to new technologies both at device and architecture level. Keeping in view the significance of non Von Neumann architecture and post CMOS technologies, a crossbar based NOR logic gate was designed using CNTFETs and ReRAM devices to facilitate in-memory computing. ReRAM based logic circuits using MAGIC and IMPLY have been already implemented but this work focuses on ratioed logic based ReRAM-CNTFET design because of its better compatibility with crossbar architecture which is conceived to be a promising candidate for in-memory computing. In this work, hybrid CNTFET (carbon nanotube field effect transistor) -ReRAM (resistive random access memory) based NOR logic gate has been designed and its performance has been compared with its CMOS-ReRAM based counterpart. The results yielded from HSPICE simulations depict better performance in terms of power dissipation, power delay product(PDP) and temperature variation. © 2021 IEEE.
%K Carbon nanotube field effect transistors; Carbon nanotubes; CMOS integrated circuits; Computation theory; Computer circuits; Integrated circuit design; Logic gates; Memory architecture; Network architecture, CMOS technology; Crossbar; Crossbar networks; HSPICE; Performance; Performances analysis; Power-delay products; Pseudo NMOS; Ratioed logic; Scalings, RRAM