TY  - JOUR
EP  - 2023
SN  - 13492543
N1  - cited By 6
SP  - 2017
TI  - An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC
AV  - none
JF  - IEICE Electronics Express
A1  - Assaad, M.
A1  - Alser, M.
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-83455166667&doi=10.1587%2felex.8.2017&partnerID=40&md5=285a218b1330d127a326056fd37459ce
VL  - 8
Y1  - 2011///
N2  - In this paper, an all-digital serializer circuit based on a novel frequency and delay locked-loop (F/DLL) clock multiplier is presented. The advantages of the proposed F/DLL are that, it simultaneously generates a high frequency signal from a low frequency reference signal and synchronizes the two signals without jitter accumulation issue. Moreover, it can be easily adapted for different FPGA families as well as implemented as an integrated circuit. The proposed serializer circuit is used as a part of a SERDES in inter-module communication in system-on-chip (SoC). The simulation and experimental results confirm the performance of the serializer with the proposed clock multiplier. © IEICE 2011.
IS  - 23
ID  - scholars1439
KW  - Clock multiplier; Clock multipliers; High frequency signals; Inter-Module communication; Jitter accumulation; Low frequency; Serializers; System-On-Chip
KW  -  Application specific integrated circuits; Clocks; Communication; Field programmable gate arrays (FPGA); Multiplying circuits; Phase locked loops
KW  -  Programmable logic controllers
ER  -