TY  - CONF
N2  - Scaling of CMOS technology is degrading the reliability of upcoming microelectronic devices. When the circuit design enters the nanoscale dimensions, the inputs have more influence on the circuit's reliability due to the circuit's internal noises and gate errors. In this paper, we will model the deterministic inputs probabilistically and analyze their effect on the reliability of digital circuits. The analysis is based on the Bayesian networks error modelling scheme. The simulations are based on MATLAB and show the important relationships among different deterministic inputs and their reliabilities. The results show the range of reliability values obtained by changing the deterministic input probability values. © 2011 IEEE.
CY  - Kota Kinabalu, Sabah
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-83755194852&doi=10.1109%2fRSM.2011.6088322&partnerID=40&md5=f8cc5c601e8111db02c89c1d2ddf38db
AV  - none
ID  - scholars1430
SN  - 9781612848464
TI  - Improvement in reliability by changing the deterministic inputs of nanoscale circuits
Y1  - 2011///
A1  - Khalid, U.
A1  - Anwer, J.
A1  - Singh, N.
A1  - Hamid, N.H.
A1  - Asirvadam, V.S.
EP  - 197
KW  - Circuit designs; CMOS technology; deterministic Inputs; Gate errors; Internal noise; Micro-electronic devices; Nanoscale circuits; Nanoscale dimensions
KW  -  Bayesian networks; CMOS integrated circuits; Electric network analysis; Integrated circuit manufacture; MATLAB; Microelectronics; Nanotechnology; Reliability
KW  -  Digital circuits
N1  - cited By 1; Conference of 2011 IEEE Regional Symposium on Micro and Nano Electronics, RSM 2011 ; Conference Date: 28 September 2011 Through 30 September 2011; Conference Code:87842
SP  - 195
ER  -