%A U. Khalid
%A J. Anwer
%A N. Singh
%A N.H. Hamid
%A V.S. Asirvadam
%T Determination of sensitive inputs of nanoscale digital circuits using Bayesian network analysis
%J 2011 IEEE Regional Symposium on Micro and Nanoelectronics, RSM 2011 - Programme and Abstracts
%R 10.1109/RSM.2011.6088320
%X The reliability of digital circuits is greatly distorted as the VLSI design cycle enters into nanoscale arena. In the past, the inputs of digital circuits were considered deterministic but shifting of transistor technology into nanoscale dimensions has made their behaviour totally probabilistic. The reason is that logic level voltages suffer from a number of fluctuations due to the effect of signal noise and transient faults. These inputs are now considered as distributed inputs and there is a need to model them probabilistically. This paper shows how to model these inputs and their effects on digital circuits' reliability. For the analysis covered in this paper, we will determine sensitive inputs of few test circuits followed by their justification and anticipated effects. © 2011 IEEE.
%D 2011
%L scholars1429
%P 186-189
%O cited By 1; Conference of 2011 IEEE Regional Symposium on Micro and Nano Electronics, RSM 2011 ; Conference Date: 28 September 2011 Through 30 September 2011; Conference Code:87842
%C Kota Kinabalu, Sabah
%K Digital inputs; Logic levels; Nano scale; Nanoscale dimensions; Sensitive inputs; Signal noise; Test circuit; Transient faults; VLSI design, Bayesian networks; Electric network analysis; Nanotechnology; Probabilistic logics; Reliability; Reliability analysis; VLSI circuits, Digital circuits