TY  - CONF
A1  - Khalid, U.
A1  - Anwer, J.
A1  - Singh, N.
A1  - Hamid, N.H.
A1  - Asirvadam, V.S.
EP  - 189
Y1  - 2011///
SN  - 9781612848464
TI  - Determination of sensitive inputs of nanoscale digital circuits using Bayesian network analysis
ID  - scholars1429
SP  - 186
KW  - Digital inputs; Logic levels; Nano scale; Nanoscale dimensions; Sensitive inputs; Signal noise; Test circuit; Transient faults; VLSI design
KW  -  Bayesian networks; Electric network analysis; Nanotechnology; Probabilistic logics; Reliability; Reliability analysis; VLSI circuits
KW  -  Digital circuits
N1  - cited By 1; Conference of 2011 IEEE Regional Symposium on Micro and Nano Electronics, RSM 2011 ; Conference Date: 28 September 2011 Through 30 September 2011; Conference Code:87842
N2  - The reliability of digital circuits is greatly distorted as the VLSI design cycle enters into nanoscale arena. In the past, the inputs of digital circuits were considered deterministic but shifting of transistor technology into nanoscale dimensions has made their behaviour totally probabilistic. The reason is that logic level voltages suffer from a number of fluctuations due to the effect of signal noise and transient faults. These inputs are now considered as distributed inputs and there is a need to model them probabilistically. This paper shows how to model these inputs and their effects on digital circuits' reliability. For the analysis covered in this paper, we will determine sensitive inputs of few test circuits followed by their justification and anticipated effects. © 2011 IEEE.
AV  - none
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-83755194863&doi=10.1109%2fRSM.2011.6088320&partnerID=40&md5=9680e32f8f2aa77a5302030d5ca4e092
CY  - Kota Kinabalu, Sabah
ER  -