eprintid: 13686
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/01/36/86
datestamp: 2023-11-10 03:28:15
lastmod: 2023-11-10 03:28:15
status_changed: 2023-11-10 01:51:45
type: article
metadata_visibility: show
creators_name: Al-Shatari, M.O.A.
creators_name: Hussin, F.A.
creators_name: Aziz, A.A.
creators_name: Witjaksono, G.
creators_name: Tran, X.-T.
title: FPGA-Based Lightweight Hardware Architecture of the PHOTON Hash Function for IoT Edge Devices
ispublished: pub
keywords: Economic and social effects; Field programmable gate arrays (FPGA); Hash functions; Integrated circuit design; Iterative methods; Logic Synthesis; Photons, Cryptographic algorithms; Cryptographic engines; Cryptographic hash functions; Hardware architecture; Internet of thing (IOT); Maximum operating frequency; Performance trade-off; Resourceconstrained devices, Internet of things
note: cited By 12
abstract: The design of cryptographic engines for the Internet of Things (IoT) edge devices and other ultralightweight devices is a crucial challenge. The emergence of such resource-constrained devices raises significant challenges to current cryptographic algorithms. PHOTON is an ultra-lightweight cryptographic hash function targeting low-resource devices. The currently implemented hardware architectures of PHOTON hash function utilize a large amount of resources and have low operating frequencies with a low rate of throughputs. Maximum operating frequency and throughput of PHOTON architecture can be improved but at the cost of larger area utilization. Therefore, to improve the area-performance trade-offs of PHOTON hash function, an iterative architecture is implemented in this work. The concern is with the most lightweight version of PHOTON hash function with the hash size of 80 bits. It is implemented and verified on several Xilinx and Altera Field Programmable Gate Array (FPGA) devices using their synthesis and simulation tools. Low-cost and high-processing FPGA devices were both considered. The design is optimized for performance, whereas the area utilization is also taken into consideration. The overall performance and logic utilization are benchmarked with the existing implementations. The results show an improvement rate of 10.26 to 51.04 in the speed performance and a reduction rate of 7.55 to 60.64 in area utilization compared to existing implementations of PHOTON hash functions. © 2013 IEEE.
date: 2020
publisher: Institute of Electrical and Electronics Engineers Inc.
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85097331319&doi=10.1109%2fACCESS.2020.3038219&partnerID=40&md5=53fb328d6e3680cf34a01ff5c5785a05
id_number: 10.1109/ACCESS.2020.3038219
full_text_status: none
publication: IEEE Access
volume: 8
pagerange: 207610-207618
refereed: TRUE
issn: 21693536
citation:   Al-Shatari, M.O.A. and Hussin, F.A. and Aziz, A.A. and Witjaksono, G. and Tran, X.-T.  (2020) FPGA-Based Lightweight Hardware Architecture of the PHOTON Hash Function for IoT Edge Devices.  IEEE Access, 8.  pp. 207610-207618.  ISSN 21693536