TY - CONF AV - none PB - Institute of Electrical and Electronics Engineers Inc. SP - 21 TI - Design of Double-Precision Fully-Programmable Computational Unit for FPGA and ASIC KW - Application specific integrated circuits; Computer software reusability; Field programmable gate arrays (FPGA); Functions; Polynomials KW - Computational units; Digital hardware; Double precision; Environmental variations; Fully programmables; Polynomial functions; Sensing algorithms; Technology nodes KW - Integrated circuit design Y1 - 2020/// N2 - The sensing algorithm of many high-precision sensors is implemented in Field Programmable Gate Arrays (FPGAs) because such devices meet most of the algorithm requirements. But to enhance sensors' performance, it is often required to compensate for their output against environmental variations. This compensation requires implementing polynomial functions in some variables corresponding to the environmental variations. This paper presents a low-cost design for double-precision, reusable, and flexible computational unit for implementing such polynomial functions in digital hardware. The design can be directly used for any FPGA and even for Application-Specific Integrated Circuit (ASIC) development. In the case of ASIC design, it also features the required flexibility to handle sensor to sensor polynomial variations. The design has been verified through simulation for different FPGAs and 350nm technology node ASIC. The design has also been implemented in Spartan-6 FPGA to compensate sensors' output in real-time. © 2020 IEEE. SN - 9781728163307 EP - 26 ID - scholars12817 A1 - Sajjad, M. A1 - Yusoff, M.B.Z. A1 - Ahmed, M. UR - https://www.scopus.com/inward/record.uri?eid=2-s2.0-85096951763&doi=10.1109%2fiCCECE49321.2020.9231146&partnerID=40&md5=5dc31a82b33fecfff5b58fb43873ab43 N1 - cited By 3; Conference of 3rd International Conference on Computing, Electronics and Communications Engineering, iCCECE 2020 ; Conference Date: 17 August 2020 Through 18 August 2020; Conference Code:164385 ER -