relation: https://khub.utp.edu.my/scholars/12817/
title: Design of Double-Precision Fully-Programmable Computational Unit for FPGA and ASIC
creator: Sajjad, M.
creator: Yusoff, M.B.Z.
creator: Ahmed, M.
description: The sensing algorithm of many high-precision sensors is implemented in Field Programmable Gate Arrays (FPGAs) because such devices meet most of the algorithm requirements. But to enhance sensors' performance, it is often required to compensate for their output against environmental variations. This compensation requires implementing polynomial functions in some variables corresponding to the environmental variations. This paper presents a low-cost design for double-precision, reusable, and flexible computational unit for implementing such polynomial functions in digital hardware. The design can be directly used for any FPGA and even for Application-Specific Integrated Circuit (ASIC) development. In the case of ASIC design, it also features the required flexibility to handle sensor to sensor polynomial variations. The design has been verified through simulation for different FPGAs and 350nm technology node ASIC. The design has also been implemented in Spartan-6 FPGA to compensate sensors' output in real-time. © 2020 IEEE.
publisher: Institute of Electrical and Electronics Engineers Inc.
date: 2020
type: Conference or Workshop Item
type: PeerReviewed
identifier:   Sajjad, M. and Yusoff, M.B.Z. and Ahmed, M.  (2020) Design of Double-Precision Fully-Programmable Computational Unit for FPGA and ASIC.  In: UNSPECIFIED.     
relation: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85096951763&doi=10.1109%2fiCCECE49321.2020.9231146&partnerID=40&md5=5dc31a82b33fecfff5b58fb43873ab43
relation: 10.1109/iCCECE49321.2020.9231146
identifier: 10.1109/iCCECE49321.2020.9231146