relation: https://khub.utp.edu.my/scholars/1209/
title: Optimization of processor architecture for image edge detection filter
creator: Osman, Z.E.M.
creator: Hussin, F.A.
creator: Ali, N.B.Z.
description: In this paper, a dedicated edge detection processor architecture based on field programmable gate arrays is presented. The architecture is an optimization of the Sobel edge detection filter, specifically focusing on the reduction of the computation time. The proposed architecture reduces the number of calculations required for the edge detection process by enhancing the data reuse, i.e. minimizing the frequency of memory access. Direct hardware implementation as proposed by previous works require most image pixels to be read from memory up to six times and transferred into the Sobel edge detection processor. In our work, we try to reduce the number of pixels read therefore affecting tremendous potential speed suitable for the embedded video processing applications. © 2010 IEEE.
date: 2010
type: Conference or Workshop Item
type: PeerReviewed
identifier:   Osman, Z.E.M. and Hussin, F.A. and Ali, N.B.Z.  (2010) Optimization of processor architecture for image edge detection filter.  In: UNSPECIFIED.     
relation: https://www.scopus.com/inward/record.uri?eid=2-s2.0-77954488285&doi=10.1109%2fUKSIM.2010.123&partnerID=40&md5=aac57d3da22b4cb5a2d2347aa1e7ed59
relation: 10.1109/UKSIM.2010.123
identifier: 10.1109/UKSIM.2010.123