eprintid: 11522
rev_number: 2
eprint_status: archive
userid: 1
dir: disk0/00/01/15/22
datestamp: 2023-11-10 03:26:02
lastmod: 2023-11-10 03:26:02
status_changed: 2023-11-10 01:15:28
type: article
metadata_visibility: show
creators_name: Khanday, F.A.
creators_name: Kant, N.A.
creators_name: Dar, M.R.
creators_name: Zulkifli, T.Z.A.
creators_name: Psychalinos, C.
title: Low-Voltage Low-Power Integrable CMOS Circuit Implementation of Integer- and Fractional-Order FitzHugh-Nagumo Neuron Model
ispublished: pub
keywords: Analog integrated circuits; CMOS integrated circuits; Electric grounding; Field programmable gate arrays (FPGA); Neural networks; Neurons; Semiconductor device manufacture; Timing circuits, Field programmable analog arrays; Fitzhugh Nagumo neurons; Fractional order; Hardware neural networks; Low power implementation; Neuron model; Performance parameters; Taiwan semiconductor manufacturing companies, Low power electronics
note: cited By 36
abstract: The low-voltage low-power sinh-domain (SD) implementations of integer- and fractional-order FitzHugh-Nagumo (FHN) neuron model have been introduced in this paper. Besides, the effect of fractional-orders on the external excitation current and dynamics of the neuron has been examined in this paper. The proposed SD designs of FHN neuron model have the benefits of: 1) low-voltage operation; 2) integrability, due to resistor-less design and the employment of only grounded components; 3) electronic tunability of performance parameters; and 4) low-power implementation due to the inherent properties of SD technique. HSPICE simulator tool and Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan 130-nm CMOS process was used to evaluate and verify the correct functioning of the model. In addition, to experimentally verify the operation of the proposed fractional-order FHN neuron model, field-programmable analog array (FPAA) implementation of the model has been presented, and the proper functioning of the model has been verified. To the best of the authors' knowledge, this is the first paper that describes the electronic realization of the fractional-order FHN neuron model. In addition, it is the first time that the FPAA implementation of any fractional-order neuron model has been presented. © 2012 IEEE.
date: 2019
publisher: Institute of Electrical and Electronics Engineers Inc.
official_url: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85056593018&doi=10.1109%2fTNNLS.2018.2877454&partnerID=40&md5=1730158fc16cbe64139f740830d4486d
id_number: 10.1109/TNNLS.2018.2877454
full_text_status: none
publication: IEEE Transactions on Neural Networks and Learning Systems
volume: 30
number: 7
pagerange: 2108-2122
refereed: TRUE
issn: 2162237X
citation:   Khanday, F.A. and Kant, N.A. and Dar, M.R. and Zulkifli, T.Z.A. and Psychalinos, C.  (2019) Low-Voltage Low-Power Integrable CMOS Circuit Implementation of Integer- and Fractional-Order FitzHugh-Nagumo Neuron Model.  IEEE Transactions on Neural Networks and Learning Systems, 30 (7).  pp. 2108-2122.  ISSN 2162237X