%R 10.1109/RSM46715.2019.8943495
%D 2019
%L scholars11414
%J Proceedings of the 2019 IEEE Regional Symposium on Micro and Nanoelectronics, RSM 2019
%O cited By 7; Conference of 2019 IEEE Regional Symposium on Micro and Nanoelectronics, RSM 2019 ; Conference Date: 21 August 2019 Through 23 August 2019; Conference Code:156451
%K Buffer layers; Electric fields; Hardening; Nanoelectronics; Radiation hardening, ATLAS software; Atmospheric applications; Electrical characteristic; MOSFET structures; N-buffer layers; Power UMOSFET; Silvaco; Single-event burnouts, Power MOSFET
%X An enhanced structure for Single-Event Burnout (SEB) hardening in trench gate shielded power UMOSFET is presented in this work. The proposed power MOSFET structure includes an n-type region wrapping p+ shielded region underneath the gate trench and adds an n-buffer layer between the epitaxial layer and substrate. With SILVACO ATLAS software, the standard and hardened UMOSFET are investigated to prove that the added n-region spreads out the electrons to the downward direction and the buffer layer could provide a leaking path of hole current and improve the device's tolerance to single-event burnout. The simulation results show that the electric field in the hardened structure is reduced when compared to a standard structure, and the SEB survivability also increased significantly. Meanwhile, there is no impact on the enhanced electrical characteristics namely threshold and breakdown voltages. Hence, for space and atmospheric applications, this power MOSFET provides high SEB survivability. © 2019 IEEE.
%P 91-94
%A S. Krishnamurthy
%A R. Kannan
%A F.A. Hussin
%A E.A. Yahya
%I Institute of Electrical and Electronics Engineers Inc.
%T Enhanced Trench Shielded Power UMOSFET for Single Event Burnout Hardening