@article{scholars10919,
            year = {2018},
         journal = {Communications in Computer and Information Science},
       publisher = {Springer Verlag},
           pages = {87--100},
            note = {cited By 1; Conference of 4th Latin American Conference on High Performance Computing, CARLA 2017 ; Conference Date: 20 September 2017 Through 22 September 2017; Conference Code:209259},
          volume = {796},
             doi = {10.1007/978-3-319-73353-1{$_6$}},
           title = {Parallel batch self-organizing map on graphics processing unit using CUDA},
        keywords = {Computer graphics; Computer graphics equipment; Conformal mapping; Program processors; Self organizing maps, Best matching units; Clustering; CUDA; GPGPU; Gpu parallelization; High dimensional datasets; Parallel SOM; Training algorithms, Graphics processing unit},
             url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-85040232044&doi=10.1007\%2f978-3-319-73353-1\%5f6&partnerID=40&md5=855c79f6bc9bbf3e845fb2ec81210fdc},
        abstract = {Batch Self-Organizing Map (Batch-SOM) is being successfully used for clustering and visualization of high-dimensional datasets in a wide variety of domains. Although the structure of its training algorithm has a high potential for parallelization, focus of the previous efforts has been on the original Step-wise SOM. This gap is due to the facts that Batch-SOM requires some extra precautions (specially in its initialization phase), and it took quite a while since its introduction that researchers affirmed the desirability of using it in practice over the Step-wise SOM. Hence, the purpose of this paper is to propose a GPU parallelization model and implementation for the Batch-SOM using CUDA. The most computationally expensive parts of its training algorithm (such as steps to compute distance between each data vector and neuron, and determining the Best Matching Unit based on minimum distance) are identified and mapped on GPU to be processed in parallel. The proposed implementation shown significant speedups of 11{\~A}? and 5{\~A}? compared to the sequential and parallel CPU implementations respectively. {\^A}{\copyright} Springer International Publishing AG 2018.},
            issn = {18650929},
          author = {Daneshpajouh, H. and Delisle, P. and Boisson, J.-C. and Krajecki, M. and Zakaria, N.},
            isbn = {9783319733524}
}