@article{scholars10282,
             doi = {10.11591/ijeecs.v10.i3.pp1036-1044},
          number = {3},
          volume = {10},
            note = {cited By 0},
           title = {Fine-grained overhead characterisation of cross-ISA DBTO for multicore processor},
            year = {2018},
           pages = {1036--1044},
       publisher = {Institute of Advanced Engineering and Science},
         journal = {Indonesian Journal of Electrical Engineering and Computer Science},
             url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-85044576410&doi=10.11591\%2fijeecs.v10.i3.pp1036-1044&partnerID=40&md5=b1095cd4f2ee40b0762fd29af0a787fa},
        abstract = {The emergence of modern portable software, start to behaved hybrid shortlong running combined applications, in which an active apps may invoked others to fulfill task requirements. Thus the implementation of Dynamic Translation and Optimisation (DBTO) into heterogeneous multicore system-on-chip (SoC) will require careful re-study, to ensure efficient usage of most available cores. In order to improve efficiency in supporting this Instruction Set Architecture (ISA) diversity of computing platforms, mix modes of statically and dynamically Binary Translation and Optimization system, or DBTO, need to utilize concurrent compilation techniques, to better service the combined applications processing. This research deep dived into finer-grained DBTO overhead analysis, to provide categorization and characterization of overhead sources in breakdown stages during concurrent instruction processing. A dual-engine of translation and optimization is constructed for finer managemnt of start-up overheads. Helper functions, i.e. LoadLink/StoreCondition (LL/SC) are derived from atomic instructions, to create multiple helper thread supported by multiple host cores, for better instruction translation and optimization operation concurrently. Our experiment platform, evaluated through PARSEC-3.0 benchmark suite, shows performance improvement approaching 2.0x for apps based programs and 1.25x for kernel based programs, for x86 to X86-64 emulation. This technique possess great potential and serve as research based platform for future binary translation technique development, including adaptive method. {\^A}{\copyright} 2018 Institute of Advanced Engineering and Science. All rights reserved.},
            issn = {25024752},
          author = {Ooi, J.-O. and Hussin, F. A. and Zakaria, M. N.}
}