TY  - CONF
AV  - none
CY  - Kuala Lumpur
ID  - scholars1014
TI  - Joint and Marginal Probability analyses of Markov Random Field networks for digital logic circuits
KW  - Belief propagation algorithm; Joint probability; Marginal probability; Markov random field; Probabilistic computation
KW  -  Algorithms; Design; Digital circuits; Fault tolerance; Integrated circuits; Logic circuits; Probability; Quality assurance; Switching circuits
KW  -  Integrated circuit manufacture
N2  - With the device scaling up to nano-level, the integrated circuits are expected to face high computing error rates. This increased rate is the outcome of random and dynamic noise injected in the circuit which becomes more vulnerable due to low supply voltages and extremely small transistor dimensions. Markov Random Field (MRF) modelling is one approach to achieve noise-tolerance in integrated circuit design. As a general overview of fault-tolerance, we start with comparing on-going techniques for fault-tolerant design. Later, we explain the two basic terminologies of MRF i.e. Joint and Marginal Probability followed by their computation for M3 module of C432 Interrupt Controller (as our test circuit). The contribution of this paper is the derivation of circuit design rules based on the conclusions obtained by these two probability analyses.
N1  - cited By 5; Conference of 2010 International Conference on Intelligent and Advanced Systems, ICIAS 2010 ; Conference Date: 15 June 2010 Through 17 June 2010; Conference Code:84196
SN  - 9781424466238
Y1  - 2010///
A1  - Anwer, J.
A1  - Khalid, U.
A1  - Singh, N.
A1  - Hamid, N.H.
A1  - Asirvadam, V.S.
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-78650383554&doi=10.1109%2fICIAS.2010.5716131&partnerID=40&md5=0a84acef4763296c40580fbdfadeff22
ER  -