TY  - JOUR
SP  - 1153
TI  - Bio-inspired network on chip having both guaranteed throughput and best effort services using fault-tolerant algorithm
N1  - cited By 0
AV  - none
EP  - 1162
SN  - 19314973
PB  - John Wiley and Sons Inc.
KW  - Computer system recovery; Distributed computer systems; Fault tolerance; Network architecture; Packet switching; Programmable logic controllers; Quality of service; Routers; Servers; Throughput; Video signal processing
KW  -  Best effort services; Fault tolerant algorithms; Fault tolerant technique; Fault-tolerant; Fault-tolerant mechanism; Guaranteed throughputs; Network on chip (NoC); Quality of Service parameters
KW  -  Network-on-chip
ID  - scholars10112
N2  - Network-on-chip (NoC) is a communication framework for multiple cores connected together in a system-on-chip (SoC). Different NoC architectures have provided quality of service (QoS) parameters of best effort (BE) and guaranteed throughput (GT). GT services are provided by having a dedicated connection using circuit switching or connection-oriented mechanism of packet switching. GT traffic is usually preferred for real-time traffic such as video processing and multimedia applications. BE services are provided using packet switching. Cache updates is an example of BE noncritical traffic. In this paper, we implement a novel biologically inspired fault-tolerant algorithm that provides both GT and BE QoS. In order to provide fault tolerance, the router architectures is also updated. The bio-inspired, fault-tolerant techniques are a novel way to provide fault tolerance in NoC. Faults in the NoC arise as the size of the devices are shrinking on the NoC, which include the router, links, and processing elements (PEs), to accommodate the complex communication requirements of applications. The proposed NoC's fault-tolerant methods (synaptogenesis and sprouting) are adapted from the biological brain's robust fault-tolerant mechanisms. From the experimental results, the throughput and bandwidth utilization are dropped by 3.55 and 4.87, respectively, during the recovery from faults. The interflit arrival time and packet network latency are increased by only 7.03 and 22.60, respectively, during the recovery from faults. The algorithm also performs as efficiently as the traditional fault-tolerant techniques. © 2018 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. © 2018 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.
IS  - 8
VL  - 13
UR  - https://www.scopus.com/inward/record.uri?eid=2-s2.0-85045185473&doi=10.1002%2ftee.22678&partnerID=40&md5=dac206d93d520b84693ed3930f310a33
JF  - IEEJ Transactions on Electrical and Electronic Engineering
A1  - Sethi, M.A.J.
A1  - Hussin, F.A.
A1  - Hamid, N.H.
Y1  - 2018///
ER  -