A performance comparison study on multiplier designs

Lee, C.Y.H. and Hiung, L.H. and Lee, S.W.F. and Hamid, N.H. (2010) A performance comparison study on multiplier designs. In: UNSPECIFIED.

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Abstract

This study investigates the relative performances of Array, Wallace, Dadda and Reduced Area multipliers for several synthesis optimization modes. All multiplier designs were modeled in Verilog HDL and synthesized based on the TSMC 0.35-micron ASIC Design Kit standard cell library. Performance data was extracted after logic synthesis in LeonardoSpectrum for Area, Speed and Auto optimization modes. Findings indicate that the Dadda multiplier may not always have a speed advantage over Wallace's design, but depends greatly on the optimization effects in gate-level synthesized design. Results for comparison of 32�32-bit variants indicate that the Wallace scheme is well suited for high-speed applications, independent of area constraints, while the Dadda and Reduced Area designs deliver best speed when synthesized to minimize area or logic usage.

Item Type: Conference or Workshop Item (UNSPECIFIED)
Additional Information: cited By 8; Conference of 2010 International Conference on Intelligent and Advanced Systems, ICIAS 2010 ; Conference Date: 15 June 2010 Through 17 June 2010; Conference Code:84196
Uncontrolled Keywords: Array multipliers; Dadda multipliers; Logic synthesis; Reduced area multiplier; Wallace multiplier, Design; Digital arithmetic; Electric batteries; Integrated circuits; Optimization, Frequency multiplying circuits
Depositing User: Mr Ahmad Suhairi UTP
Date Deposited: 09 Nov 2023 15:49
Last Modified: 09 Nov 2023 15:49
URI: https://khub.utp.edu.my/scholars/id/eprint/915

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